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| Integrated Circuit Systems, Inc. ICS83841 20 BIT, DDR SDRAM 2:1 MUX FEATURES * 40 low skew single-ended DIMM ports * 1 SSTL-2 compatible select input * Maximum Switching Speed: 3ns * Output skew: 180ps (maximum) * ron = 20 (typical) * Full 2.5V supply modes * 0C to 70C ambient operating temperature GENERAL DESCRIPTION The ICS83841 is a 20 Bit, DDR SDRAM 2:1 MUX and is a member of the HiPerClockSTM family of HiPerClockSTM High Performance Clock Solutions from ICS. The device has 20 host lines and each host line can be passed to 2 data ports. The host/data ports are compatible with single-ended SSTL-2 and the device operates from a 2.5V supply. ICS Guaranteed low output skew makes the ICS83841 ideal for demanding applications which require well defined performance and repeatability. SIMPLIFIED SCHEMATIC LOGIC DIAGRAM DH0 ron Sw Sw DA0 DB0 DHx DAx or DBx RPD DH19 ron Sw Sw DA19 DB19 S S SW PIN ASSIGNMENT 1 A B C D E F G H J K DB17 DA18 DB18 DA19 DB19 DA0 DB0 DA1 DB1 DA2 2 DA17 DH17 DH18 GND DH19 DH0 GND DH1 DH2 DB2 3 DB16 DH16 4 DB15 DA16 5 DA15 DH15 GND 6 DB14 DH14 GND 7 DA14 DB13 8 DA13 DH13 9 DB12 DH12 DH11 GND 10 DA12 DB11 DA11 DB10 DA10 DB9 DA9 DB8 DA8 DB7 REV. A APRIL 2, 2004 ICS83841 72-Ball TFBGA 6mm x 6mm x 1.2mm package body H Package Top View S VDD GND DH3 DA3 DB3 DA4 DH4 DB4 GND DH5 DA5 DA6 DB5 VDD VDD DH10 DH9 GND DH8 DH6 DB6 DH7 DA7 83841BH www.icst.com/products/hiperclocks.html 1 Integrated Circuit Systems, Inc. ICS83841 20 BIT, DDR SDRAM 2:1 MUX TABLE 1. PIN DESCRIPTIONS Number E8, F3, F8 C5, C6, D2, D9, G2, G9, H5, H6 E3 B2, B3, B5, B6, B8, B9, C2 C9, E2, E9, F2, F9, H2, H9, J2, J3, J5, J6, J8, J9 A2, A5, A7, A8, A10, B1, B4, C10, D1, E10, F1, G10, H1, J7, J10, K1, K3, K4, K6, K9 A1, A3, A4, A6, A9, B7, B10, C1, D10, E1, F10, G1, H10, J1, J4, K2, K5, K7, K8, K10 Name VDD GND S DH17, DH16, DH15, DH14, DH13, DH12, DH18, DH11, DH19, DH10, DH0, DH9, DH1, DH8, DH2, DH3, DH4, DH5, DH6, DH7 DA17, DA15, DA14, DA13, DA12, DA18, DA16, DA11, DA19, DA10, DA0, DA9, DA1, DA6, DA8, DA2, DA3, DA4, DA5, DA7 DB17, DB16, DB15, DB14, DB12, DB13, DB11, DB18, DB10, DB19, DB9, DB0, DB8, DB1, DB3, DB2, DB4, DB5, DB6, DB7 Type Description Power Positive supply pins. Power Power supply ground. Control Input. Selects Host Input Por t function per Table 3. Por t Host por ts. Por t DIMM por ts. Por t DIMM por ts. TABLE 2. PIN CHARACTERISTICS Symbol Parameter CIN CON Control Pin Capacitance Channel on Capacitance Test Conditions VI = 0V or VDD VIN = 1.5V Minimum Typical Maximum 5 10 Units pF pF TABLE 3. FUNCTION TABLE Control Input S L H Function Host Por t = B DIMM Por ts A DIMM Por t = 140 to GND Host Por t = A DIMM Por ts B DIMM Por t = 140 to GND 83841BH www.icst.com/products/hiperclocks.html 2 REV. A APRIL 2, 2004 Integrated Circuit Systems, Inc. ICS83841 20 BIT, DDR SDRAM 2:1 MUX ABSOLUTE MAXIMUM RATINGS Supply Voltage, VDD Inputs, VI Ports DC Input Clamp Current, IIK Package Thermal Impedance, JA Storage Temperature, TSTG -50mA 50.04C/W (0 mfps) -65C to 150C -0.5V to +3.3V -0.3V to VDD + 0.3 V NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Character- istics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = 2.5V 0.2V, TA = 0C TO 70C Symbol Parameter VDD IDD Positive Supply Voltage Power Supply Current Test Conditions Minimum 2.3 Typical 2.5 20 Maximum 2.7 Units V A TABLE 4B. DC CHARACTERISTICS, VDD = 2.5V 0.2V, TA = 0C TO 70C Symbol Parameter VIH VIL VIK IL Input High Voltage Input Low Voltage Input Clamp Voltage S Input Leakage Current Host Por t DIMM Por t rON On Resistance; NOTE 1 S S VDD = 2.3V; II = -18mA VDD = 2.5V; VI = VDD or GND; S = VDD S = GND for IIL(test) VDD = 2.5V; VA = 0.8V; VB = 1.0V 16 20 Test Conditions Minimum 1.6 0.9 -1.2 100 100 100 30 Typical Maximum Units V V V A A A 16 20 30 VDD = 2.5V; VA = 1.7V; VB = 1.5V NOTE 1: Measured by the current between the Host and the DIMM terminals at the indicated voltages on each side of the switch. TABLE 5. AC CHARACTERISTICS, VDD = 2.5V 0.2V, TA = 0C TO 70C Symbol Parameter Test Conditions Minimum Typical Maximum Units Propagation Delay; From DHx or DAx/DBx tPD 125 240 ps NOTE 1, 3 to DAx/DBx or DHx Output From S to 1.2 ns t EN Enable Time DHx or DAx/DBx Output From S to 1.2 ns tDIS Disable Time DHx or DAx/DBx Output Skew; Any Por t to any Por t 180 ps tOSK NOTE 2, 3 NOTE 1: Measured from VDD/2 of the input to VDD/2 of the output. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDD/2. NOTE 3: Not production tested, guaranteed by characterization. 83841BH www.icst.com/products/hiperclocks.html 3 REV. A APRIL 2, 2004 Integrated Circuit Systems, Inc. ICS83841 20 BIT, DDR SDRAM 2:1 MUX PARAMETER MEASUREMENT INFORMATION VDD = 1.25V 0.1V V DD SCOPE DAx, DBx V DD 2 LVCMOS GND Qx V DD DAy, DBy 2 tsk(o) -1.25V 0.1V This circuit is used for test purposes only, not intended for application use. 2.5V OUTPUT LOAD AC TEST CIRCUIT OUTPUT SKEW 2.5V 1.25V Input Rising Edge Skew 1.25V Output 1.25V 0V FallingEdge Skew VOH 1.25V VOL S (Low-level enabling) 2.5V 1.25V 1.25V 0V tPZH Output DAx/DBx (See Note) 1.25V tPHZ VOH VOH - 0.15V VOL NOTE: The output is high except when disabled by the S control. RISING & FALLING EDGE SKEW 3-STATE OUTPUT ENABLE/DISABLE TIMES DAx VDD 2 DHx VDD 2 DBx VDD 2 tsk(o) DAx/DBx t PD VDD 2 BANK SKEW 83841BH PROPAGATION DELAY www.icst.com/products/hiperclocks.html 4 REV. A APRIL 2, 2004 Integrated Circuit Systems, Inc. ICS83841 20 BIT, DDR SDRAM 2:1 MUX RELIABILITY INFORMATION TABLE 6. JAVS. AIR FLOW TABLE FOR A 72-BALL TFBGA JA by Velocity (Millimeter Feet per Second) 0 Two-Layer PCB, JEDEC Standard Test Boards 50.04C/W 1 43.18C/W 2 41.17C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs. TRANSISTOR COUNT The transistor count for ICS83841 is: 261 83841BH www.icst.com/products/hiperclocks.html 5 REV. A APRIL 2, 2004 Integrated Circuit Systems, Inc. ICS83841 20 BIT, DDR SDRAM 2:1 MUX 72-BALL TFBGA PACKAGE OUTLINE - H SUFFIX FOR A TABLE 7. PACKAGE DIMENSIONS JEDEC VARIATION ALL DIMENSIONS IN MILLIMETERS FBGA SYMBOL A A1 b D D1 E E1 e MINIMUM NOMINAL MAXIMUM 72 Balls, 6x6mm, 10x10 Pattern 1.0 0.165 0.25 1.1 0.2 0.3 6.00 BSC 4.50 BSC 6.00 BSC 4.50 BSC 0.50 BSC 1.2 0.235 0.35 REFERENCE DOCUMENT: JEDEC PUBLICATION 95, MO-195 83841BH www.icst.com/products/hiperclocks.html 6 REV. A APRIL 2, 2004 Integrated Circuit Systems, Inc. ICS83841 20 BIT, DDR SDRAM 2:1 MUX TABLE 8. ORDERING INFORMATION Part/Order Number ICS83841BH ICS83841BHT ICS83841BHLF ICS83841BHLFT Marking ICS83841BH ICS83841BH ICS3841BLF ICS3841BLF Package 72-Ball TFBGA 72-Ball TFBGA on Tape and Reel 72-Ball, Lead Free, TFBGA 72-Ball, Lead Free, TFBGA on Tape and Reel Count TBD 2500 TBD 2500 Temperature 0C to 70C 0C to 70C 0C to 70C 0C to 70C The aforementioned trademark, HiPerClockSTM is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries. While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 83841BH www.icst.com/products/hiperclocks.html 7 REV. A APRIL 2, 2004 |
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